1. Field of the Invention
The present invention relates to a phase locked loop (hereinafter referred to as xe2x80x9cPLLxe2x80x9d) circuit and, in particular, to a lock detector that always detects and outputs as to whether a phase difference between an input signal and an output signal is not more than a predetermined value.
2. Description of the Background Art
On a PLL circuit, it takes much time that the phase of a returning output signal is synchronized with the phase of an input signal. Therefore, in order to detect whether the phase difference between the input signal and the returning output signal is not more than a predetermined value, a lock detector monitoring phase synchronization is usually disposed on the PLL circuit. Disposing the lock detector also enables detecting as to whether the phase difference exceeds the predetermined value due to disturbance and the like, during the operation of the PLL circuit.
As a conventional PLL circuit with a lock detector, there is a technology disclosed in Japanese Patent Application Laid Open No. 10-70457 (1998). FIG. 18 illustrates the configuration of this PLL circuit.
Referring to FIG. 18, this PLL circuit comprises: a phase comparator 1 that performs a phase comparison between an input signal f1 and a feedback signal f2 that is a divided output signal; a charge pump circuit 2 that changes the pulse width according to the output of the phase comparator 1, and outputs pulse; a loop filter circuit 3 that integrates the output pulse of the charge pump circuit 2, and outputs the result as an analog voltage signal Vc; a voltage-controlled oscillator 4 that changes the oscillation frequency according to the value of the analog voltage signal Vc, and outputs an output signal fo; a frequency divider 5 that divides the output signal fo, and outputs a feedback signal f2; and a lock detector 9 that detects whether the input signal f1 and the feedback signal f2 are in phase synchronization, based on output signals Pu and Pd from the phase comparator 1.
The voltage-controlled oscillator 4 is formed by a ring counter, for example. The analog voltage signal Vc from the loop filter 3 is applied to the ring counter, and the oscillation frequency of the ring counter changes according to the value of the analog voltage signal Vc.
On this PLL circuit, the feedback signal f2 is controlled so as to be synchronized with the input signal f1. When the phase of the feedback signal f2 is behind of the phase of the input signal f1, a pulse signal of a width corresponding to such a phase difference is outputted from the phase comparator 1, as a pulse signal Pu. At this time, the value of the analog voltage signal Vc increases by the functions of the charge pump circuit 2 and loop filter 3. Upon receipt of this analog voltage signal Vc, the voltage-controlled oscillator 4 functions to increase the frequency of the output signal fo and hasten the phase of the feedback signal f2.
On the other hand, when the phase of the feedback signal f2 is ahead of the phase of the input signal f1, a pulse signal of a width corresponding to such a phase difference is outputted from the phase comparator 1, as an output signal Pd. At this time, the value of the analog voltage signal Vc decreases by the functions of the charge pump circuit 2 and loop filter 3. Upon receipt of this analog voltage signal Vc, the voltage-controlled oscillator 4 functions to decrease the frequency of the output signal fo and delay the phase of the feedback signal f2.
As used herein, the output signal Pu of the phase comparator 1 is a pulse signal that changes to xe2x80x9cHixe2x80x9d (assuming xe2x80x9cHi-activexe2x80x9d in the description) at the rise of the pulse of the input signal f1. The output signal Pd of the phase comparator 1 is a pulse signal that changes to xe2x80x9cHixe2x80x9d (assuming xe2x80x9cHi-activexe2x80x9d in the description) at the rise of the pulse of the feedback signal f2. One of the output signals Pu and Pd which changes to xe2x80x9cHixe2x80x9d at a later time, falls to xe2x80x9cLowxe2x80x9d immediately after the mentioned rise, and the other changes to xe2x80x9cLowxe2x80x9d together with the fall of the former.
The lock detector 9 comprises an exclusive NOR circuit 6 on which, upon receipt of the output signals Pu and Pd from the phase comparator 1, the exclusive OR of the two signals is inverted and outputted; a delay circuit 7 on which the output signal Pc of the exclusive NOR circuit 6 is delayed and outputted; and a D-flip-flop circuit 8. The D-flip-flop circuit (hereinafter referred to as xe2x80x9cD-FFxe2x80x9d) 8 comprises a clock input terminal T to which an output signal Pc of the exclusive NOR circuit 6 is inputted; a signal input terminal D to which an output signal Pa of the delay circuit 7 is inputted; and an output terminal Q from which a lock detecting signal SL is outputted.
The delay circuit 7 is formed by a ring counter, for example. An analog voltage signal Vc from the loop filter 3 is applied to the ring counter. The delay amount of respective delay stages forming the ring counter changes depending on the value of the analog voltage signal Vc.
FIGS. 19 and 20 are diagrams illustrating timing charts of signals in the respective parts of this PLL circuit. FIG. 19 shows the case that the phase of the input signal f1 is ahead of the phase of the feedback signal f2 (i.e., an asynchronous case). FIG. 20 shows the case that phase of the input signal f1 substantially coincides with the phase of the feedback signal f2 (i.e., a synchronous case).
Regardless of whether the feedback signal f2 and input signal f1 are delayed or not, the exclusive NOR circuit 6 generates and outputs a pulse signal Pc having a pulse width Pw1 that corresponds to the phase difference between the two signals, by using the output signals Pu and Pd of the phase comparator 1 (It is supposed to be substantially synchronous in FIG. 20, however, assume there is a slight phase difference in the rise of the output signals Pu and Pd). The delay circuit 7 outputs a pulse signal Pa that is behind of the pulse signal Pc by a predetermined time Td1.
The D-FF circuit 8 fetches the state of a pulse signal Pa when the pulse signal Pc transits from xe2x80x9cLowxe2x80x9d to xe2x80x9cHixe2x80x9d, and it outputs, as a lock detecting signal SL, xe2x80x9cHixe2x80x9d when the pulse signal Pa is xe2x80x9cHixe2x80x9d, and xe2x80x9cLowxe2x80x9d when the pulse signal Pa is xe2x80x9cLowxe2x80x9d.
If a pulse width Pw1 of the pulse signal Pc is larger than a delay time Td1 of the delay circuit 7, the pulse signal Pa is in xe2x80x9cLowxe2x80x9d level at t0 at which the pulse signal Pc transits from xe2x80x9cLowxe2x80x9d to xe2x80x9cHixe2x80x9d level. Therefore, the D-FF circuit 8 fetches the xe2x80x9cLowxe2x80x9d state, and outputs the xe2x80x9cLowxe2x80x9d level indicating that phase is asynchronous, as a lock detecting signal SL.
If the pulse width Pw1 of the pulse signal Pc is smaller than the delay time Td1 of the delay circuit 7, the pulse signal Pa is in xe2x80x9cHixe2x80x9d level at t1 at which the pulse signal Pc transits from xe2x80x9cLowxe2x80x9d to xe2x80x9cHixe2x80x9d level. Therefore, the D-FF circuit 8 fetches xe2x80x9cHixe2x80x9d state, and outputs xe2x80x9cHixe2x80x9d level indicating that phase is synchronous, as a lock detecting signal SL.
Thus, the lock detector 9 detects phase synchronous or asynchronous, based on the delay time Td1.
FIG. 21 is a circuit diagram illustrating a configuration of a phase comparator 1 disclosed in Japanese Patent Application Laid Open No. 56-169931 and U.S. Pat. No. 4,322,643. The phase comparator 1 is made up of inverter circuits 40 to 43, two-input NAND circuits 46 to 51, three-input NAND circuits 52, 53, and a four-input NAND circuits 56. In this circuit configuration, when an input signal f1 and a feedback signal f2 are both in xe2x80x9cLowxe2x80x9d state, output signals Pu and Pd are both in xe2x80x9cLowxe2x80x9d state.
When an input signal f1 firstly transits from xe2x80x9cLowxe2x80x9d to xe2x80x9cHixe2x80x9d, signal change propagates in the following order: the inverter circuits 40, two-input NAND circuit 46, three-input NAND circuit 52, and inverter circuit 42, so that the output signal Pu transits from xe2x80x9cLowxe2x80x9d to xe2x80x9cHixe2x80x9d. After transition of the input signal f1, when a feedback signal f2 transits from xe2x80x9cLowxe2x80x9d to xe2x80x9cHixe2x80x9d, signal change propagates in the following order: the inverter circuit 41, two-input NAND circuit 47, three-input NAND circuit 53, and inverter circuit 43, so that the output signal Pd transits from xe2x80x9cLowxe2x80x9d to xe2x80x9cHixe2x80x9d. Subsequently, signal change propagates in the following order: the inverter circuit 41, two-input NAND circuit 47, four-input NAND circuit 56, three-input NAND circuits 52 and 53, and inverter circuits 42 and 43, so that both of the output signals Pu and Pd transit from Hixe2x80x9d to xe2x80x9cLowxe2x80x9d.
On the other hand, when a feedback signal f2 firstly transits from xe2x80x9cLowxe2x80x9d to xe2x80x9cHixe2x80x9d, signal change propagates in the following order: the inverter circuit 41, two-input NAND circuit 47, three-input NAND circuit 53, and inverter circuit 43, so that the output signal Pd transits from xe2x80x9cLowxe2x80x9d to xe2x80x9cHixe2x80x9d. After transition of the feedback signal f2, when an input signal f1 transits from xe2x80x9cLowxe2x80x9d to xe2x80x9cHixe2x80x9d, signal change propagates in the following order: the inverter circuit 40, two-input NAND circuit 46, three-input NAND circuit 52, and inverter circuit 42, so that the output signal Pu transits from xe2x80x9cLowxe2x80x9d to xe2x80x9cHixe2x80x9d. Subsequently, signal change propagates in the following order: the inverter circuit 40, two-input NAND circuit 46, four-input NAND circuit 56, three-input NAND circuits 52 and 53, and inverter circuits 42 and 43, so that both of the output signals Pu and Pd transit from Hixe2x80x9d to xe2x80x9cLowxe2x80x9d.
With the foregoing configuration, on the phase comparator 1 there are generated the output signals Pu and Pd which are pulse signals of a width corresponding to the phase difference in the rise of the input signal f1 and feedback signal f2.
However, the conventional PLL circuit having the mentioned configuration suffers from the following three problems.
First Problem:
When the input signal f1 and feedback signal f2 approach phase synchronization, the phase difference therebetween is slight, and the pulse width Pw1 of the pulse signal Pc is narrowed. Therefore, in some cases the D-FF circuit 8 fails to accurately fetch the state of the pulse signal Pa. For instance, referring to FIG. 20, although the pulse signal Pc is activated on receipt of the output signals Pu and Pd, the D-FF circuit 8 is incapable of recognizing that the pulse signal Pc is activated because the pulse width Pw1 is narrow. In the case, the lock detecting signal SL is held at xe2x80x9cLowxe2x80x9d level. That is, there is the possibility that the incorrect content is outputted as a lock detecting signal.
Second Problem:
In the event that the input signal f1 stops suddenly in the synchronous state (i.e., the input of the input signal f1 is interrupted for any reason such as contact failure or disconnection on a circuit substrate), the pulse width Pw1 of the pulse signal Pc continues increasing (see FIG. 22, which shows the case that the input signal f1 stops at time point LP). As a result, the pulse signal Pc does not transit from xe2x80x9cLowxe2x80x9d to xe2x80x9cHixe2x80x9d, and the D-FF circuit 8 continues applying xe2x80x9cHixe2x80x9d level indicating phase synchronization to the lock detecting signal SL, although no phase synchronization is established.
Third Problem:
On the mentioned PLL circuit, in the progress that an output signal is synchronous with an input signal, the phase difference therebetween becomes zero momentarily in some cases. Even in this case, the pulse width of the pulse signal Pc is narrow. Therefore, the output indicating phase synchronization is temporarily applied, although synchronization is not completed. FIG. 23 is a diagram illustrating how frequency changes with time in the progress that the feedback signal f2 is synchronous with the input signal f1. On a PLL circuit of which damping factor is set to a small value, a feedback signal f2 oscillates and gradually approaches the frequency and phase of the input signal f1. Therefore, even at the point indicated by mark xe2x80x9c◯xe2x80x9d at which synchronization is incomplete, frequency momentarily coincides with phase. In this case, the conventional lock detector 9 judges it synchronous state, although synchronization is incomplete.
It is an object of the present invention to provide a lock detector that does not output a lock detecting signal of incorrect content when approaching phase synchronization, or when an input signal stops suddenly, or when phase difference becomes zero momentarily in the progress that an output signal is synchronized with an input signal, as well as a PLL circuit including this lock detector.
According to a first aspect of the invention, a lock detector includes: a reset signal output part to activate a reset signal when there is a phase difference of not less than a predetermined value between first and second pulse signals that repeat oscillation; and a signal output part that outputs a lock detecting signal indicating synchronization of the first and second pulse signals and deactivates said lock detecting signal when the reset signal is activated.
In the first aspect of the invention, when the phase difference between the first and second pulse signals is not less than a predetermined value, the reset signal is activated and the lock detecting signal is not activated. Therefore, by setting such that the signal output part activates, in principle, the lock detecting signal unless the reset signal is activated, there is no possibility that the signal output part erroneously outputs the content of the lock detecting signal as asynchronous.
According to a second aspect of the invention, a phase locked loop circuit includes: a lock detector of the first aspect; a phase comparator to compare phases of the first and second pulse signals, taking one of these signals as an input signal and taking the other as a feedback signal; a filter that outputs a control signal based on a comparison result of the phase comparator; and an oscillation circuit that outputs the feedback signal based on the control signal.
In the second aspect of the invention, a phase locked loop circuit that does not output the lock detecting signal of incorrect content can be obtained by disposing the lock detector according to the first aspect.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.